FIG. 1 illustrates, by example, a block diagram of a conventional radio communication transceiver 100 (hereinafter referred to as "transceiver"). The transceiver 100 enables a mobile or portable subscriber unit to communicate with a base station (not shown), for example, over radio frequency (RF) channels in a radio communication system (not shown). The base station thereafter provides communications with a landline telephone system (not shown) and other subscriber units. An example of a subscriber unit having the transceiver 100 is a cellular radiotelephone.
The transceiver 100 of FIG. 1 generally includes an antenna 101, a duplex filter 102, a receiver 103, a transmitter 105, a reference frequency signal source 107, a receive (Rx) phase locked loop (PLL) frequency synthesizer 108, a transmit (Tx) PLL frequency synthesizer 109, a processor 110, an information source 106, and an information sink 104.
The interconnection of the blocks of the transceiver 100 and operation thereof is described as follows. The antenna 101 receives a RF signal 119 from the base station for filtering by the duplex filter 102 to produce an RF received signal at line 111. The duplex filter 102 provides frequency selectivity to separate the RF received signal at line 111 and the RF transmit signal at line 113. The receiver 103 is coupled to receive the RF received signal at line 111 and operative to produce a received baseband signal at line 112 for the information sink 104. The reference frequency signal source 107 provides a reference frequency signal at line 115. The Rx PLL frequency synthesizer 108 is coupled to receive the reference frequency signal at line 115 and information on a data bus 118 and operative to produce a receiver tune signal at line 116 to tune the receiver 103 to a particular RF channel. Likewise, the Tx PLL frequency synthesizer 109 is coupled to receive the reference frequency signal at line 115 and information on the data bus 118 and operative to produce a transceiver tune signal at line 117 to tune the transmitter 105 to a particular RF channel. The processor 110 controls the operation of the Rx PLL frequency synthesizer 108, the Tx PLL frequency synthesizer 109, the receiver 103, and the transmitter 105 via the data bus 118. The information source 106 produces a baseband transmit signal at line 114. The transmitter 105 is coupled to receive the baseband transmit signal at line 114 and operative to produce the RF transmit signal at line 113. The duplex filter 102 filters the RF transmit signal at line 113 for radiation by the antenna 101 as a RF signal 120.
The RF channels in a cellular radiotelephone system, for example, include voice and signaling channels for transmitting and receiving (hereinafter referred to as "transceiving") information between the base station and the subscriber units. The voice channels are allocated for transceiving voice information. The signaling channels, also referred to as control channels, are allocated for transceiving data and signaling information. It is through these signaling channels that the subscriber units gain access to the cellular radiotelephone system and are assigned a voice channel for further communication with the landline telephone system. In cellular radiotelephone systems capable of transceiving wide band data on the signaling channels, the frequency spacing of the signaling channels is a multiple of the frequency spacing of the voice channels.
In some cellular radiotelephone systems, the transceiver 100 and the base station intermittently transceive information therebetween on the signaling channel. One such system, for example, an interleaved data signaling method to synchronize the intermittent information. In this type of system, keeping the transceiver 100 fully powered during the entire time that the transceiver 100 is tuned to the signaling channel unnecessarily drains the transceiver's battery during those times when the information is not received. Therefore, portions of the transceiver 100 can be powered off to prolong battery life when the transceiver is not transceiving information. Further, portions of the transceiver 100 can be powered off to prolong battery life when the signal quality is good enough such that further repetition of the same information is not needed. Intermittently powering on and off, i.e. enabling and disabling, the transceiver 100 during its receive operation is called discontinuous receive (DRX) mode of operation. In the DRX mode of operation, quickly enabling and disabling the portions of transceiver 100 increases the savings in battery life.
FIG. 2 illustrates, by example, a block diagram of a conventional phase locked loop (PLL) frequency synthesizer for use in the transceiver 100 of FIG. 1. The general structure of the PLL frequency synthesizer of FIG. 2 is the same for both the Rx PLL frequency synthesizer 108 and the Tx PLL frequency synthesizer 109.
The PLL frequency synthesizer 108 or 109 of FIG. 2 generally includes a reference divider 201, for discussion purposes, and a PLL 212. The PLL 212 generally includes a phase detector 202, a loop filter 203, a voltage controlled oscillator 204, and a loop divider 205. The reference divider 201 receives a reference frequency signal on line 115.
The interconnection of the blocks of the PLL frequency synthesizer 108 or 109 of FIG. 2 is described as follows. The reference divider 201 is coupled to receive the reference signal at line 115 and the data bus 118 and operative to produce a divided reference frequency signal at line 206. The phase detector 202 is coupled to receive a divided reference frequency signal at line 206 and a feedback signal at line 209, and operative to produce a phase error signal at line 207. The loop filter 203 is coupled to receive the phase error signal 207, and operative to produce a filtered signal at line 208. The voltage controlled oscillator 204 is coupled to receive the filtered signal at line 208 and operative to produce an output frequency signal at line 116 or 117. The loop divider 205 is coupled to receive the output frequency signal at line 116 or 117, and operative to produce the feedback signal at line 209. The loop divider 205 and the reference divider 201 are coupled to receive programming information at the data bus 118.
The operation of the PLL frequency synthesizer 108 or 109 of FIG. 2 is described as follows. The PLL 212 is a circuit which produces the output frequency signal at line 116 or 117 synchronized to the reference frequency signal at line 115. The output frequency signal at line 116 or 117 is synchronized or "locked" to the reference frequency signal at line 115 when the frequency of the output frequency signal at line 116 or 117 has a predetermined frequency relationship to the frequency of the reference frequency signal at line 115. Under locked conditions, the 212 PLL typically provides a constant phase difference between the reference frequency signal at line 115 and the output frequency signal at line 116 or 117. The constant phase difference may assume any desired value including zero. Should a deviation in the desired phase difference of such signals develop, i.e., should a phase error at line 207 develop due to, e.g., variation in either the frequency of the reference frequency signal at line 115 or programmable parameters of the PLL via the data bus 118, the PLL adjusts the frequency of the output frequency signal at line 116 or 117 to drive the phase error at line 207 toward the value of the constant phase difference.
PLL's are characterized by a loop bandwidth. For some applications it is desirable to vary the loop bandwidth of the PLL under certain conditions such as, for example, when the frequency of the reference frequency signal at line 115 changes or when the programmable parameters of the PLL via the data bus 118 changes. Appropriately varying the loop bandwidth advantageously provides shorter lock time, improved noise, and lower spurious signals.
One general problem with varying the loop bandwidth of the PLL 212 includes determining when to vary the loop bandwidth. Determining when to vary the loop bandwidth directly affects the time required for the PLL 212 to reach a desirable locked condition. It is generally desirable for the PLL 212 to reach its locked condition quickly. If the locked condition of the PLL 2 12 is not reached quickly, noise may be generated or information may be lost.
One particular problem in implementing the discontinuous mode in the transceiver 100 is the recovery (relock) time needed by the PLL 212 to re-establish phase and frequency lock of the carrier frequency, particularly if the PLL 212 must cycle rapidly between the enabled and disabled modes in order to provide the maximum current savings. Further, in the discontinuous mode, the relock time of the PLL 212 can be degraded by current leakage on the filtered signal at line 208 which causes the frequency of the VCO 204 to drift during the disabled portion of the discontinuous mode. The PLL 212 does not replenish the charge on the loop filter 203 and compensate for the leakage while it is disabled. The greater the drift, the more the PLL 212 must compensate its frequency, as well as phase, when it is re-enabled and the longer is the relock time.
A solution provided by the prior art to reduce the recovery time in the discontinuous mode has been to use a synchronization scheme, when the PLL frequency synthesizer 108 or 109 is re-enabled, to reduce or eliminate the phase drift that occurred when the PLL frequency synthesizer 108 or 109 was disabled. A disadvantage with this solution is that, while it does correct for the phase drift, the normal operation of the PLL 212 must still correct for the frequency drift which occurs due to real-world leakage on the filtered signal at line 208.
Another particular problem exists in the transceiver 100 employing a PLL frequency synthesizer 108 or 109 which must rapidly tune between channels in a radio frequency band. If the PLL frequency synthesizer 108 or 109 does not have a sufficiently short lock time during a change in output frequency, the transceiver 100 can miss receiving data or produce errors in transmitted data.
One solution provided by the prior art to reduce lock time has been to increase the bandwidth of the PLL 212. The disadvantage of this solution is that it leads to increased spurious signals and noise at the output of VCO 204 because of the reduced filtering of the wider bandwidth.
Another solution provided by the prior art to reduce lock time in the PLL frequency synthesizer 108 or 109 has been to increase the frequency of the divided reference frequency signal 206 to the PLL 212 so as to increase the loop bandwidth of PLL 212. The disadvantage of this solution is two-fold. First, this solution requires a large increase in the frequency of the divided reference frequency 206 to provide a significant increase in the loop bandwidth because the loop bandwidth increases as the square root of M, where M is the increase in the frequency of the divided reference frequency signal 206 to the PLL 212. Second, the PLL 212 locks at a frequency of the output frequency signal 116 or 117 that is near but not precisely at the final desired frequency. The divided reference frequency 206 and the loop bandwidth must then be switched back to their initial values and the PLL 212 must lock to its final desired frequency. Therefore, two locking cycles are needed and that leads to a long lock time.
Accordingly, there is a need for an apparatus and method for operating a phase locked loop frequency synthesizer responsive to radio frequency channel spacing which advantageously provides for faster lock time and lower noise at the output of the PLL frequency synthesizer.